chenjinbu
|
ffc5786ed5
|
材料表自动生成
|
2025-09-22 09:25:18 +08:00 |
|
chenjinbu
|
2c5bf00d85
|
材料表自动生成，布置图下来多选和默认块图纸
|
2025-09-22 09:21:04 +08:00 |
|
CHEN-ZW\acer
|
0d7752d821
|
信号预分配功能
|
2025-09-15 18:35:41 +08:00 |
|
CHEN-ZW\acer
|
50f581ba36
|
Merge branch 'main' of http://27.154.35.18:7053/yuxingheng/009_DI-Elec
|
2025-09-12 12:03:48 +08:00 |
|
CHEN-ZW\acer
|
8a2c73eabb
|
信号管理，io分配bug
|
2025-09-12 12:03:20 +08:00 |
|
chenjinbu
|
4eddfe1f59
|
布置图输入值改成可输入的下拉框，ini操作异常修改，布置图加载修改
|
2025-09-10 10:57:20 +08:00 |
|
chenjinbu
|
93967b9e1d
|
1
|
2025-09-09 09:06:55 +08:00 |
|
CHEN-ZW\acer
|
516581840d
|
1.存在送审时间不提示
|
2025-09-09 08:58:50 +08:00 |
|
CHEN-ZW\acer
|
a9fb4be5d1
|
信号管理外部加载dll报错bug
|
2025-09-05 12:03:25 +08:00 |
|
CHEN-ZW\acer
|
dec2a796e8
|
信号管理
|
2025-09-04 18:28:02 +08:00 |
|
chenjinbu
|
d5d39ed68d
|
布置图自动绘制
|
2025-09-02 11:27:57 +08:00 |
|
CHEN-ZW\acer
|
7bd39c4653
|
电气前端提交
|
2025-08-15 18:00:11 +08:00 |
|
CHEN-ZW\acer
|
8b0f0f76d6
|
no message
|
2025-08-15 17:34:50 +08:00 |
|
CHEN-ZW\acer
|
770ab0e034
|
电气前端提交
|
2025-08-15 15:38:37 +08:00 |
|